1. Technical Field
The present invention is related to a wiring substrate and a semiconductor device. More specifically, the present invention is directed to a wiring substrate equipped with Connection pads which are joined to bumps of a semiconductor Chip in a flip chip method, and directed to a semiconductor device in which the semiconductor chip is joined to the wiring substrate in the flip chip method.
2. Description of the Related Art
Recently, packaging structures have been utilized in various sorts of fields, in which bumps are provided as external connection terminals on electronic components (for example, semiconductor chips), and the bumps are joined to connection pads provided on wiring substrates by employing joint materials in the flip chip manner.
For instance, technical ideas described in JP-A-2007-194598 and JP-A-2007-158081 have been proposed as conventional wiring substrates.
FIG. 6 is a plan view (schematic diagram) for showing one example of a wiring substrate 105 on which a semiconductor chip 101 shown in FIG. 7 is mounted in a flip chip manner. In this case, while FIG. 7 is a plan view for showing a circuit forming plane 101a of the semiconductor chip 101, when the semiconductor chip 101 is mounted on the wiring substrate 105 in the flip chip method, the mounting process is carried out in a face down manner in such a manner that the circuit forming plane 101a is located opposite to the wiring substrate 105.
Bumps (namely, outer peripheral bumps 102 and central bumps 103) made by employing Au (gold) have been formed on the circuit forming plane 101a of the semiconductor chip 101. The outer peripheral bumps 102 have been arranged on a peripheral portion of the circuit forming plane 101a (peripheral-shaped arrangement). Also, the central bumps 103 have been arranged in a center portion of the circuit forming plane 101a (area array-shaped arrangement). Conventionally, generally speaking, in semiconductor chips in which bumps are employed as external connection terminals, the below-mentioned structures are usually utilized. That is, these bumps are arranged in peripheral portions of the semiconductor chips in peripheral shapes. However, since semiconductor chips have been recently packaged in high density, total terminal numbers of these semiconductor chips are increased, so that the central bumps 103 are arranged also in the center portions of the circuit forming planes 101a. 
In connection with the arrangement, the wiring substrate 105 on which the semiconductor chip 101 is mounted in the flip chip manner has such a structure that connection pads (outer peripheral pads) 107 corresponding to the outer peripheral bumps 102 and connection pads (central pads) 108 corresponding to the central bumps 103 are arranged (refer to FIG. 6). In this structure, the connection pads (outer peripheral pads) 107 are formed on a frame-shaped opening portion 111 provided in a solder mask (resist) 110. Also, the connection pads (central pads) 108 are formed on respective opening portions 112 provided on the solder mask (resist) 110.
In this case, as structures for forming connection pads (and positioning marks which will be described later) on wiring substrates, there are an NSMD (Non-Solder Mask Defined) structure and an SMD (Solder Mask Defined) structure.
As shown in a plan view in FIG. 8A and a front sectional view in FIG. 8B (namely, sectional view, taken along line A-A in FIG. 8A), the NSMD structure corresponds to such a structure that a connection pad 131 is defined as a conductor shape within an opening portion 134 of a solder mask (resist) 133, while an inner diameter of the opening portion 134 is made larger than an outer diameter of a circular portion of the connection pad 131. It should be noted that symbol 130 indicates an insulating layer which constitutes a base.
On the other hand, as indicated in a plan view in FIG. 9A and a front sectional view in FIG. 9B (namely, sectional view, taken along line B-B in FIG. 9A), the SMD structure corresponds to such a structure that a connection pad 132 is defined based upon an opening shape (namely, shape of opening portion 135) of a solder mask (resist) 133, while an inner diameter of the opening portion 135 is made smaller than an outer diameter of a circular portion of the connection pad 132.
On the other hand, in the case that semiconductor chips are mounted on wiring substrates in the flip chip manner, positioning marks have been employed in order to join the semiconductor chips at predetermined positions. Normally, the positioning marks are formed on the wiring substrates.
Conventionally, as shown in FIG. 10, in the case that a semiconductor chip (not shown) having peripheral-shape arrayed bumps is mounted on a wiring substrate 141 in the flip chip manner, normally, an NSMD structure defined based upon a shape of a conductor (namely, connection pads 151) provided in an opening portion 154 of a solder mask 153 is employed in connection pads 151 formed on the wiring substrate 141, and also, the NSMD structure is similarly employed in a positioning mark 156. This reason is given as follows. That is, since the structure of the positioning mark 156 is made coincident with the structure of the connection pad 151, a positioning process is accurately carried out in such a manner that a center position of the bumps formed on the semiconductor chip is made coincident with a center position of the conductors (connection pads 151) provided within the opening portion 154 of the solder mask 153 formed on the wiring substrate 141.
On the other hand, as shown in FIG. 11, in the case that a semiconductor chip (not shown) having area array-shaped arrayed bumps is mounted on a wiring substrate 142 in the flip chip manner, normally, an SMD structure defined based upon shapes of openings (namely, shapes of opening portions 155) of a solder mask 153 is employed in connection pads 152 formed on the wiring substrate 142, and also, the SMD structure is similarly employed in a positioning mark 157. This reason is given as follows. That is, since the structure of the positioning mark 157 is made coincident with the structure of the connection pad 152, a positioning process is accurately carried out in such a manner that a center position of the bumps formed on the semiconductor chip is made coincident with a center position (namely, center position of exposed portions of connection pads 152) of the opening portions 155 of the solder mask 153 formed on the wiring substrate 142. It should also be noted that portions defined by broken lines in FIG. 11 indicate one example as to shapes of edge portions of the connection pads 152 covered by the solder mask 153.
As previously described, conventionally, in order to carry out the positioning processes accurately during flip-chip mounting operations, a positioning mark employs either the NSMD structure or the SMD structure in correspondence with a structure of connection pads. As a consequence, in such a case that the semiconductor chip (refer to FIG. 6) in which the bumps arranged in the peripheral shape and the bumps arranged in the area array shape are mixed with each other is mounted on a wiring substrate 143 shown in FIG. 12, the structures as to both the connection pads 151 arrayed in the peripheral shape and the connection pads 150 arrayed the area array shape are required to be unified in either the NSMD structures or the SMD structures. At the same time, a structure of a positioning mark 158 which is provided on the wiring substrate 143 is similarly required to be unified in the same NSMD, or SMD structure. Normally, the connection pads 151 arrayed in the peripheral shape within the opening portions 154 can not be formed in the SMD structure, but can be formed in the NSMD structure, since pitches (will be referred to as “pad pitches” hereinafter) of adjoining connection pads 151 are narrow. In connection to the above-described structure aspect, the connection pads 150 arrayed in the area array shape in the center portion of the wiring substrate 143, and the positioning mark 158 are required to be formed in the NSMD structures.
However, in the case that the connection pads 150 arranged in the area array shape in the central portion of the wiring substrate 143 are formed in the NSMD structure, shapes of opening portions 159 of the solder mask 153 are required to be designed to have a larger dimension than that of the solder mask 153 employing the SMD structure in order that shapes of conductors (namely, edge portions of connection pads 150) within the opening portions 159 must be exposed from front planes of the opening portions 159 (refer to FIG. 12). As a result, the below-mentioned restrictions are caused in designing aspects. That is, a power supply system line (either power supply line or ground line) of the uppermost layer of the wiring substrate 143 can be hardly formed in a plain, namely, formed in the form of a flat plate in an integral body.
The present invention is made to solve the above-described problems of the conventional technique, and therefore, has an object to provide a wiring substrate having a superior electric characteristic, to which a semiconductor chip where bumps arranged in a peripheral shape and bumps arranged in an area array shape are mixed with each other is mounted in a flip chip manner.